A brief note on Transistors and Logic Gates . Read it before a test. Try each question at the end before you open its answer.
The transistor Regions: the emitter is heavily doped, the base is thin and lightly doped, and the collector is larger and moderately doped. The arrow of the symbol is on the emitter. Currents: I E = I B + I C I_E = I_B + I_C I E = I B + I C , α = I C I E \alpha = \dfrac{I_C}{I_E} α = I E I C , β = I C I B \beta = \dfrac{I_C}{I_B} β = I B I C , β = α 1 − α \beta = \dfrac{\alpha}{1 - \alpha} β = 1 − α α . Regions of work: active (emitter forward, collector reverse, I C ≈ β I B I_C \approx \beta I_B I C ≈ β I B ), saturation (both forward, V C E ≈ 0.2 V_{CE} \approx 0.2 V C E ≈ 0.2 V), cut-off (no base current). Circuit: V C C = I C R C + V C E V_{CC} = I_C R_C + V_{CE} V C C = I C R C + V C E and V B B = I B R B + V B E V_{BB} = I_B R_B + V_{BE} V B B = I B R B + V B E , with V B E = 0.7 V_{BE} = 0.7 V B E = 0.7 V for silicon. Resistances: r i = ( Δ V B E Δ I B ) V C E r_i = \left(\dfrac{\Delta V_{BE}}{\Delta I_B}\right)_{V_{CE}} r i = ( Δ I B Δ V B E ) V C E and r o = ( Δ V C E Δ I C ) I B r_o = \left(\dfrac{\Delta V_{CE}}{\Delta I_C}\right)_{I_B} r o = ( Δ I C Δ V C E ) I B . Amplifier and switch Voltage gain: A V = − β R C r i A_V = -\dfrac{\beta R_C}{r_i} A V = − r i β R C . The output is 180 ∘ 180^\circ 18 0 ∘ out of phase. A I = β A_I = \beta A I = β and ∣ A P ∣ = β ∣ A V ∣ |A_P| = \beta |A_V| ∣ A P ∣ = β ∣ A V ∣ . Clipping: the output stays between 0.2 0.2 0.2 V and V C C V_{CC} V C C . The Q point is near V C C / 2 V_{CC}/2 V C C /2 . Switch: cut-off gives V o = V C C V_o = V_{CC} V o = V C C and saturation gives V o ≈ 0.2 V_o \approx 0.2 V o ≈ 0.2 V. Saturation needs I B ≥ V C C − 0.2 V β R C I_B \ge \dfrac{V_{CC} - 0.2\ \text{V}}{\beta R_C} I B ≥ β R C V C C − 0.2 V . The switch is a NOT gate. Oscillator: an amplifier with positive feedback and a tuned circuit, f = 1 2 π L C f = \dfrac{1}{2\pi\sqrt{LC}} f = 2 π L C 1 . Logic gates Gates: NOT A ‾ \overline{A} A , OR A + B A + B A + B , AND A ⋅ B A \cdot B A ⋅ B , NAND A ⋅ B ‾ \overline{A \cdot B} A ⋅ B , NOR A + B ‾ \overline{A + B} A + B , XOR A ⊕ B A \oplus B A ⊕ B . Remember: NAND is 0 0 0 only for 1 , 1 1, 1 1 , 1 . NOR is 1 1 1 only for 0 , 0 0, 0 0 , 0 . XOR is 1 1 1 when the inputs differ. n n n inputs give 2 n 2^n 2 n rows. De Morgan: A + B ‾ = A ‾ ⋅ B ‾ \overline{A + B} = \overline{A} \cdot \overline{B} A + B = A ⋅ B and A ⋅ B ‾ = A ‾ + B ‾ \overline{A \cdot B} = \overline{A} + \overline{B} A ⋅ B = A + B . Universal gates: NAND alone, or NOR alone, can make every gate. NOT is one gate, AND is two, OR is three. A worked example A transistor has β = 100 \beta = 100 β = 100 , V C C = 9 V_{CC} = 9 V C C = 9 V, R B = 300 k Ω R_B = 300\ \text{k}\Omega R B = 300 k Ω and R C = 1.0 k Ω R_C = 1.0\ \text{k}\Omega R C = 1.0 k Ω . Find V C E V_{CE} V C E .
The base current. I B = 9 V − 0.7 V 300 k Ω = 27.7 μ A I_B = \dfrac{9\ \text{V} - 0.7\ \text{V}}{300\ \text{k}\Omega} = 27.7\ \mu\text{A} I B = 300 k Ω 9 V − 0.7 V = 27.7 μ A . The collector current. I C = 100 × 27.7 μ A = 2.77 I_C = 100 \times 27.7\ \mu\text{A} = 2.77 I C = 100 × 27.7 μ A = 2.77 mA. The voltage. V C E = 9 V − 2.77 mA × 1.0 k Ω = 6.23 V_{CE} = 9\ \text{V} - 2.77\ \text{mA} \times 1.0\ \text{k}\Omega = 6.23 V C E = 9 V − 2.77 mA × 1.0 k Ω = 6.23 V. The transistor is active. Practise with new numbers
Check yourself Which gate is made by tying the two inputs of a NAND gate together? Stuck? Show a hint Show the answerThe input of a transistor inverter changes from 0 0 0 V to 5 5 5 V. What happens to the output? Stuck? Show a hint Show the answerAn amplifier has a voltage gain of − 150 -150 − 150 . What are the size and the phase of the output for an input of 4.0 4.0 4.0 mV? Stuck? Show a hint Show the answerSources NCERT Physics Class 12, Semiconductor Electronics: Materials, Devices and Simple Circuits. Horowitz and Hill, The Art of Electronics, third edition.